In recent years, a digital technology has made an outstanding progress, which is accompanied by an increasing demand for enhanced precision of an A (analog)/D (digital) conversion device that converts an analog signal into a digital signal.
As literatures showing examples in which an A/D conversion circuit is corrected simultaneously with continuous A/D conversion, there are Patent Literature 1 and Non Patent Literature 1.
As illustrated in FIG. 1, an A/D conversion device described in Patent Literature 1 includes at least two A/D conversion circuits ADC1 and ADC2, and performs calibration through the use of a reference voltage signal generated in a reference voltage generation unit 10. For example, when one A/D conversion circuit ADC1 is connected to an analog input signal AIS by a switching circuit 11 operating under the control of a control unit 1, the other A/D conversion circuit ADC2 is connected to a reference voltage generation unit 10. When such switching is performed at a predetermined time interval, the two A/D conversion circuits ADC1 and ADC2 alternately convert the analog input signal AIS and the reference voltage signal from the reference voltage generation unit 10. The control unit 1 causes a storage unit 12 to store an average value of conversion characteristics information based on digital values converted by the A/D conversion circuits (converted digital values with respect to the reference voltage signal). A digital processing circuit 13 corrects a converted value through the use of the average value of the converted digital values obtained as described above, to thereby enhance precision of correction to the A/D conversion circuits ADC1 and ADC2. The digital processing circuit 13 outputs a corrected digital output signal DOS.
Next, an entire configuration and a calibration method of an A/D conversion device described in Non Patent Literature 1 are described with reference to FIGS. 2 and 3A to 3C.
The A/D conversion device described in Non Patent Literature 1 includes two A/D conversion circuits 20A and 20B, and reference voltage generation circuits respectively combined with the A/D conversion circuits 20A and 20B. One of the A/D conversion circuits, herein, the A/D conversion circuit 20A, includes a preamplifier unit 21A formed of a plurality of preamplifiers, and a comparator unit 25A formed of a plurality of comparators corresponding to the plurality of preamplifiers. A resistor column 22A formed of a plurality of resistors R, R0, R1, R2, . . . , R8 connected in series is connected to the A/D conversion circuit 20A. A negative potential −Vref of a reference voltage source is connected to one end side of the resistor column 22A, and a positive potential +Vref of the reference voltage source is connected to the other end side of the resistor column 22A. Thus, voltages (different values) generated by voltage dividing are input to one input terminal of each preamplifier from a connection point (node) between the resistors R0 and R1, a connection point between the resistors R1 and R2, . . . , a connection point between the resistors R7 (not shown) and R8. More specifically, the resistor column 22A and the reference voltage source that applies the negative potential −Vref and the positive potential +Vref as reference voltages function as a reference voltage generation unit. The analog input signal AIS is input to the other input terminal of each preamplifier.
The other A/D conversion circuit, herein, the A/D conversion circuit 20B, also has the same configuration (preamplifier unit 21B, comparator unit 25B) as that of the A/D conversion circuit 20A. However, the reference voltage generation circuit on the A/D conversion circuit 20B side has a function of applying a voltage shifted by 1LSB (least significant bit) with respect to the negative potential −Vref and the positive potential +Vref. Therefore, switches 24-1 and 24-2 for switching terminals A and B are respectively connected to one end side and the other end side of a resistor column 22B formed of a plurality of resistors R0, R1, R2, . . . , R8 connected in series. Further, when the switches 24-1 and 24-2 are placed on the terminal A side, the positive potential +Vref and the negative potential −Vref of the reference voltage source are connected to both ends of the resistor column 22B, and the resistors R is connected in series to the negative potential side end portion of the resistor column 22B. On the other hand, when the switches 24-1 and 24-2 are placed on the terminal B side, a positive potential +Vref+1LSB and a negative potential −Vref+1LSB of another reference voltage source are connected to both ends of the resistor column 22B, and the resistor R is connected in series to the positive potential side end portion of the resistor column 22B.
Note that, each of the preamplifiers connected to the input sides of the respective comparators can perform adjustment of an output offset.
A digital processing unit 26 subjects outputs of the plurality of comparators to digital processing and outputs digital values as a digital output signal DOS.
A calibration method is performed as follows. The same analog input signal AIS is converted simultaneously by the two A/D conversion circuits 20A and 20B, to thereby make calibration based on the non-correlation of both pieces of the output data. For example, it is assumed that output signals of the A/D conversion circuits 20A and 20B are different pieces of converted data due to fluctuations between circuits or the like (FIG. 3A). In this case, a threshold value of a comparator is adjusted equivalently by adjusting an output offset of one preamplifier of the A/D conversion circuits 20A and 20B. Pieces of the converted data output from the A/D conversion circuits 20A and 20B are matched through the above-mentioned adjustment. However, the linearity of A/D conversion cannot be corrected only by these adjustments, and hence, a step of the relation with a digital output code converted with respect to an analog input voltage does not have an equal interval but has non-linear characteristics, which does not mean that calibration has been made (FIG. 3B).
Then, the switches 24-1 and 24-2 are switched so as to change the reference voltage to be applied to the other A/D conversion circuit 20B by 1LSB, and data conversion (A/D conversion) is performed based on the reference voltage shifted by 1LSB (one step). Data conversion is repeated under two conditions, in which the reference voltage is not shifted and the reference voltage is shifted. At this time, two pieces of the output data obtained by comparison with two reference voltages have no correlation, and the digital processing unit 26 performs averaging based on the two pieces of the converted data and also performs compensation for linearity precision successively. At this time, during the compensation, the above-mentioned output offset adjustment of a preamplifier of the comparator is used. Then, during the data conversion, two conversion errors are reduced by averaging (FIG. 3C).    Patent Literature 1: Japanese Unexamined Patent Application Publication (JP-A) No. 2008-131298    Non Patent Literature 1: Yuji Nakajima, Akemi Sakaguchi, Toshio Ohkido, Tetsuya Matsumoto, and Michio Yotsuyanagi, “A Self-Background Calibrated 6b 2.7 GS/s ADC with Cascade-Calibrated Folding-Interpolating Architecture” IEEE 2009 Symposium on VLSI Circuits, pp 266-267 (2009)